1. Field of the Invention
The present invention relates to the field of semiconductor integrated circuit (IC) manufacturing, and more particularly to a method of forming device isolation regions on a semiconductor substrate by using selective liquid-phase-deposition (LPD) of silicon dioxide.
2. Prior Art
With the continual improvement of semiconductor integrated circuit fabrication techniques, the number of devices which can be packed onto a semiconductor chip has increased greatly, while the size of the individual devices have decreased markedly. Today several million devices can be fabricated in a single chip--consider, for example, the mega-bit memory chips which are commonly used today in personal computers and in other applications. In such high-density chips, elements must be isolated properly in order to obtain good performance. The main purpose of device isolation techniques is to provide good insulation between the elements of the devices using smaller isolation area, to provide more space for more devices and their elements.
In the past, the so-called LOCal Oxidation of Silicon (LOCOS) technique has been widely used for device isolation of integrated circuit chips. According to this method, a thick oxide is grown as an isolating layer. FIGS. 1A to 1D demonstrate the prior art LOCOS technique. At first, a pad oxide layer 11 and then a silicon nitride layer 12 are formed on a silicon substrate 10. Those layers are patterned using lithography and etching techniques, providing the structure shown in FIG. 1A. After that, impurities of P type, such as boron ions, are implanted into the exposed portion of the substrate 10, to form a channel stop layer 13, as shown in FIG. 1B.
Referring to FIG. 1C, a thick field oxide 14 is then formed by thermal oxidization. Since the oxidizing speed of silicon nitride is less than that of silicon, the silicon nitride layer 12 works like a mask against thermal oxidization, so the field oxide grows only on where the substrate 10 is not covered by the silicon nitride layer 12. Finally, silicon nitride layer 12 is removed to obtain the isolation structure as shown in FIG. 1D.
The above described conventional LOCOS technique has a number of disadvantages, which become rather unacceptable when attempting to apply this technique to the fabrication of sub-micron devices. First, the oxidization of silicon does not happen only in the vertical direction but also in the horizontal direction. As a result, a part of the field oxide grows under the adjacent silicon nitride layer 12 and lifts it up, as can be seen in FIG. 1C. This is termed the "bird's beak effect" by persons skilled in the art. Secondly, due to the stresses caused by the bird's beak effect, a part of nitride in the compressed regions of silicon nitride layer 12 diffuses to adjacent tensile strained regions at the interface of the pad oxide layer 11 and the substrate 10, and forms a silicon-nitride-like region 15. In subsequent process steps of forming gate oxides, due to the mask effect of the silicon-nitride-like layer 15, the gate oxides will be thinner than they should be. It is termed the "white ribbon effect" because a white ribbon will appear at the edges of active regions under optical microscopes.
Additionally, because the volume of silicon dioxide is 2.2 times as large as that of silicon, the field oxide 14 protrudes above the surface of the silicon substrate 10, forming a non-recessed surface. Also, the channel stop layer 13 diffuses laterally during the high temperatures used to oxidize the silicon when forming the field oxide 14. This lateral diffusion reduces the width of adjacent active regions. Decreasing the width of those active regions is a disadvantage when one is trying to scale down the dimensions of the device. Furthermore, due to the lateral expansion of the field oxide 14 during oxidation, a great deal of stress occurs in the active region. Many crystalline defects are produced near the bird's beak regions, which result in an increase of junction leakage and in a reduction of the reliability of the devices.
Many new processes have been developed to solve the above-discussed disadvantages of LOCOS, such as: adding a sidewall spacer to reduce the bird's beak effect, adding a sacrificial oxide layer to eliminate the white ribbon effect, or forming a shallow trench before forming field oxide layer to obtain a flat surface. Each of these suggestions solves some of the disadvantages of LOCOS, but they also increase the complexity of entire process and, at the same time, and reduce production efficiency.
A technique called "Trench Isolation" is another approach which is used to form isolated regions. This technique comprises forming trenches on the silicon substrate by an etching procedure and filling the trenches with an insulating layer, such as a silicon dioxide layer, by chemical vapor deposition (CVD). Typically, deep narrow trenches are used to isolate one device from another, shallow trenches are used to isolate elements within a device, and wide trenches are used in areas where interconnection patterns will be deposited. Unfortunately, the conventional trench isolation technique cannot be implemented on large area openings. The insulating layer not only deposits vertically from the bottom of the trenches, but also deposits laterally from the sidewalls of the trenches. Since a typical semiconductor chip can have numerous trenches of varying widths, when the comparatively narrow trenches are filled, the comparatively wide trenches are not fully filled. If the deposition process is extended to fill the wide trenches, the field oxide formed in the narrow trenches will be too thick, causing a non-recessed surface to occur which, in turn, presents certain disadvantages during later IC processing, as is well known by those skilled in the art.